1. Field of the Invention
The present invention relates to a delay element employing a charge coupled device.
2. Background of the Invention
Delay elements using charge coupled devices (called a CCD delay element herein) are often used in color signal processing circuits for color video cameras.
In a color signal separation circuit for a signal carrier frequency separation system, for instance, red (R) and blue (B) signals are produced in the following manner. A color signal produced one horizontal scanning period before is added to or subtracted form what is produced by a color pickup element. A CCD delay element is employed to delay the color signal output by the one horizontal scanning period so as to implement the aforesaid processing.
FIG. 1 is a vertical sectional view showing the principal part of a conventional two-phase clock transfer type CCD delay element by way of example.
In FIG. 1, there is show a two-phase clock transfer type CCD delay element. A unit cell A is constituted by pair of transfer gate electrodes formed on the surface of a p.sup.- -type silicon substrate 1 and by P.sup.+- -type transfer barriers 2 formed beneath one of the transfer gate electrodes. One unit cell A receiving a clock signal .phi..sub.1 and another unit cell receiving another clock signal .phi..sub.2 are wired so that they are disposed alternately in the transfer direction. In addition, there are formed an input diode 3 and an output diode 4 composed of P.sup.+ regions. The input diode 3 is separated by input gates G.sub.1 and G.sub.2 from the input terminal of a group of unit cells A disposed in the transfer direction. Correspondingly, the output diode 4 is separated by an output gate OTG from the output terminal of the unit cell group. The input diode 3 is connected to an input terminal IN and the output diode 4 to an output terminal OUT.
FIG. 2 is a waveform chart showing the two-phase clock signals .phi..sub.1 and .phi..sub.2, whereas FIG. 3 is a graphic illustration of potential profiles of a potential well produced by the two-phase clock signals .phi..sub.1 and .phi..sub.2 at three points of time t.sub.1, t.sub.2 and t.sub.3. When a signal being delayed is supplied to the input terminal IN while the input gates G.sub.1 and G.sub.2 and the output gate OTG are held on, the potential well produced in each unit cell is allowed to provide transfer operation across the output terminal OUT as show in FIG. 3. An output signal is produced by the output terminal OUT after the lapse of the delay time determined by the number of series unit cells A disposed in the transfer direction and the periods of the two-phase clock signals .phi..sub.1 and .phi..sub.2.
The period of a transfer clock signal must be changed to effect the adjustment of delay time because the number of unit cells A is unchangeable once they have been manufactured according to standard semiconductor IC technology as far as the conventional CCD delay elements are concerned. In consideration of the accuracy required, however, it is difficult to the adjust delay time so minutely as to regulate the oscillation circuit for producing the transfer clock signals.